1. Field of the Invention
The present invention relates to a digital pulse-width control apparatus. More particularly, the present invention relates to a digital pulse-width control apparatus free from an influence of a duty cycle of a clock signal.
2. Description of Related Art
For high-speed very large scale integrated (VLSI) circuits, in order to ensure the accuracy of duty cycle of a clock, a pulse-width control apparatus is developed. According to the circuit designs, pulse-width control apparatuses are classified into digital and analog types. The digital pulse-width control apparatuses have fine resistance to noises, and have the advantages of fast locking and stable systems, so they are currently widely applied in VLSI circuits.
FIG. 1 is an architectural view of a conventional digital pulse-width control apparatus. Referring to FIG. 1, the conventional digital pulse-width control apparatus 100 includes a compensation delay line 110, a delay line 120, pulse-width generators 130 and 140, an SR flip-flop 150, a clock driver 160, an up/down counter 170, a pulse-width comparator 180, and a digital pulse-width converter 190. The digital pulse-width converter 190 detects a clock signal VOUT1, and generates a detection code C11 according to a detection result. Thus, the pulse-width comparator 180 determines the detection code C11 according to a pulse-width control information S11, and generates a counting information S12 and a locking information S13 according to the determination result. The up/down counter 170 counts up or down according to the counting information S12, so as to regulate and output a delay control code C12.
At this time, the delay line 120 transmits and inputs a clock signal VIN1 to the pulse-width generator 140 according to the delay time determined by the delay control code C12. In another aspect, taking the impact of parasitic capacitance and parasitic resistance to the delay line 120 into consideration, the input clock signal VIN1 is also transmitted to the pulse-width generator 130 through the compensation delay line 110. Then, the SR flip-flop 150 generates the output clock signal VOUT1 according to output signals of the pulse-width generators 130 and 140, and transmits the output clock signal VOUT1 back to the digital pulse-width converter 190 through the clock driver 160.
Thus, the conventional digital pulse-width control apparatus 100 forms a feedback mechanism, through which the detecting, determining, and regulating operations are repeated continuously until the output clock signal VOUT1 is locked. However, in actual applications, the range of the duty cycle of the input clock signal VIN1 is limited by the circuit characteristics of the compensation delay line 110 and the delay line 120. As the digital pulse-width converter 190 cannot find a balance between the layout area and the resolution of detection, the range of the duty cycle of the output clock signal VOUT1 is greatly limited.
FIG. 2 is an architectural view of another conventional digital pulse-width control apparatus. Referring to FIG. 2, the conventional digital pulse-width control apparatus 200 includes a half-period delay line 210 and an SR flip-flop 220. In the overall operation, the half-period delay line 210 is used to delay an input clock signal VIN2 for half a period, and then output it as a delayed clock signal VS2. Then, the SR flip-flip 220 determines positive transition points of the input clock signal VIN2 and the delayed clock signal VS2, so as to generate an output clock signal VOUT2 with a duty cycle of 50% accordingly.
The conventional digital pulse-width control apparatus 200 has been widely applied in correction circuits currently due to its high correction speed and negligible errors. However, the conventional pulse-width control apparatus 200 has an inevitable defect, that is, the duty cycle of the output clock signal VOUT2 is fixed to be 50%. Therefore, the conventional digital pulse-width control apparatus 200 cannot change the duty cycle of the output clock signal VOUT2 according to system requirements.
FIG. 3 is an architectural view of still another conventional digital pulse-width control apparatus. Referring to FIG. 3, the conventional digital pulse-width control apparatus 300 includes a clock width modulator 310, a clock buffer 320, a clock width converter 330, a comparator 340, a loop filter 350, and a frequency divider 360. The clock width modulator 310 regulates a pulse-width of an input clock signal VIN3 according to a pulse-width control code C31 generated by the loop filter 350. Then, the regulated input clock signal VIN3 is amplified by the clock buffer 320, and is converted into an output clock signal VOUT3. In another aspect, the clock width converter 330 converts a waveform of the output clock signal VOUT3 into a digital code C32. The comparator 340 compares the digital code C32 with a duty cycle control code C33, and transmits the comparison result to the loop filter 350. At this time, the loop filter 350 receives the input clock signal after the frequency division, and regulates the pulse-width control code C31 according to the comparison result generated by the comparator 340.
By repeating the detecting, determining, and regulating operations continuously, the conventional digital pulse-width control apparatus 300 finally assumes a locked state, and generates the output clock signal Vout3 accordingly. However, in actual applications, the clock width modulator 310 cannot regulate the input clock signal VIN3 of different frequencies with a same detection resolution. Therefore, the duty cycle of the clock signal Vout3 provided by the conventional digital pulse-width control apparatus 300 is in a very narrow range. Similarly, as the minimum pulse width that the clock buffer 320 can transmit is limited, the range of the duty cycle of the input clock signal VIN3 is also greatly limited.